1. Field of the Invention
The present invention generally relates to semiconductor devices and fabricating methods therefore and particularly to dielectric breakdown protection elements in such devices for preventing dielectric breakdown to occur in a functional portion of such devices and a method of manufacturing therefore.
2. Description of the Related Art
FIG. 5A is a plan view showing an example of a conventional semiconductor device exposed to irradiation of charged particles in a fabricating process. FIGS. 5B and 5C are sectional views taken along the line 5B--5B and the line 5C--5C in FIG. 5A, respectively. Referring to those figures, an oxide film 2 for isolation is formed on a silicon substrate 1. A capacitor 30 is provided on the oxide film 2. The capacitor 30 includes a first capacitor electrode layer 3 of polysilicon formed on the isolation oxide film 2. The first capacitor electrode layer 3 is covered with a capacitor dielectric layer 5 formed of an oxide film. A second capacitor electrode layer 8 of polysilicon is formed on the capacitor dielectric layer 5.
A MOS transistor 40 is also provided on the silicon substrate 1. The transistor 40 includes a gate dielectric layer 7 of an oxide formed on the substrate 1. A gate electrode 9 of polysilicon is formed on the gate dielectric layer 7. A pair of source/drain regions 10 are formed on both sides of a channel region under the gate dielectric layer 7.
FIGS. 6A to 6E are sectional views for explaining an example of a process of fabricating the semiconductor device shown in FIGS. 5A to 5C.
Referring to FIG. 6A, a thick oxide film 2 for isolation is selectively formed on a silicon substrate 1. A first capacitor electrode 3 of polysilicon is selectively formed on the isolation oxide film 2.
Referring to FIG. 6B, the first capacitor electrode 3 is covered with a capacitor dielectric layer 5 by thermal oxidation and a gate dielectric layer 7 is selectively formed by thermal oxidation on an exposed surface region of the silicon substrate 1.
Referring to FIG. 6C, a second capacitor electrode 8 of polysilicon is selectively formed on the capacitor dielectric layer 5 and a gate electrode 9 of polysilicon is selectively formed on the gate dielectric layer 7.
Referring to FIG. 6D as well as FIG. 6E as a sectional view taken along the line 6E--6E in FIG. 6D, a pair of source/drain regions 10 are formed in a surface layer of the substrate 1 by ion implantation 20 in a self-aligning manner utilizing the oxide film 2 and the gate electrode 9 as a mask pattern. Ion implantation is described in detail, for example, in a book titled "Ion Implantation" published by Wiley-Interscience Publication. On this occasion, the second capacitor electrode 8 and the gate electrode 9 are charged positively by the implanted ions. It is possible that a surface potential of a layer charged with ions becomes as high as 50V. If the charged quantity exceeds a certain value, dielectric breakdown may occur in the capacitor dielectric layer and/or the gate dielectric layer 7 as shown by arrows B. Once such dielectric breakdown occurs in the semiconductor device, the semiconductor device becomes a defective product.
As described above, the conventional semiconductor device exposed to irradiation of charged particles in its fabrication process involves disadvantages such as lowering of the yield in production or lowering of reliability of the device due to dielectric breakdown which would occur in the capacitor dielectric layer, the gate dielectric layer of the transistor or the like during irradiation of charged particles.
It may be possible to avoid the dielectric breakdown by lowering the ion implantation rate so as to allow relaxation of the charge concentration caused by the ion implantation. With the low ion implantation rate, however, it takes long time to obtain a desired impurity concentration in a pair of source/drain regions and thus production rate of semiconductor devices is lowered.
It may also be possible to avoid the dielectric breakdown by neutralizing the positive charges in the ion implanted layer with an electron shower. However, the electron shower must be generated in the ion implanting chamber and then it is difficult to obtain a stable electron shower during the ion implantation.